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| features n 20/40/50/65/80msps max sampling rate n low power dissipation C 23mw/channel at 20msps C 35mw/channel at 40msps C 41mw/channel at 50msps C 51mw/channel at 65msps C 59mw/channel at 80msps n 72.2db snr at 8mhz f in n 0.5s startup time from sleep n 15s startup time from power down n internal reference circuitry requires no external components n internal offset correction n reduced power dissipation modes available C 34mw/channel at 50msps C 71.5db snr at 8mhz f in n coarse and fne gain control n 1.8v supply voltage n serial lvds output C 12- and 14-bit output available n package alternatives C tqfp-80 C qfn-64 applications n medical imaging n wireless infrastructure n test and measurement n instrumentation general description the cdk8307 is a high performance low power octal analog-to-digital converter (adc). the adc employs internal reference circuitry, a serial control interface and serial lvds output data, and is based on a proprietary structure. an integrated pll multiplies the input sampling clock by a factor of 12 or 14, according to the lvds output setting. the multiplied clock is used for data serialization and data output. data and frame synchronization output clocks are supplied for data capture at the receiver. various modes and confguration settings can be applied to the adc through the serial control interface (spi). each channel can be powered down inde - pendently and data format can be selected through this interface. a full chip idle mode can be set by a single external pin. register settings determines the exact function of this external pin. the cdk8307 is designed to easily interface with feld-programmable gate arrays (fpgas) from several vendors. the very low startup times of the cdk8307 allow signifcant power reduction in duty-cycled systems, by utilizing the sleep mode or power down mode when the receive path is idle. block diagram serial control interface lvds lvds d1n d1p ip1 in1 adc lvds d2n d2p ip2 in2 adc lvds pll clock input digital gain digital gain digital gain d8n d8p ip8 in8 adc avdd avss dvdd dvss pd clkp clkn fclkp fclkn lclkp lclkn resetn csn sclk sdata ? ? ? ? ? ? ? ? ? cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds exar corporation www.exar.com 48720 kato road, fremont ca 94538, usa tel. +1 510 668-7000 - fax. +1 510 668-7001
?2009-2013 exar corporation 2/31 rev 1c table of contents features .................................................................. 1 applications ............................................................ 1 general description ................................................ 1 block diagram ........................................................ 1 table of contents ................................................... 2 ordering information ............................................. 3 pin confgurations .................................................. 4 pin assignments .................................................. 5-8 absolute maximum ratings ................................... 9 reliability information ........................................... 9 esd protection ........................................................ 9 recommended operating conditions .................... 9 electrical characteristics ...................................... 10 electrical characteristics C cdk8307a ............ 10-11 electrical characteristics C cdk8307b ................ 11 electrical characteristics C cdk8307c ............ 11-12 electrical characteristics C cdk8307d ............ 12-13 electrical characteristics C cdk8307e ................ 13 digital and timing electrical characteristics .. 13-14 lvds timing diagrams ......................................... 15 figure 1. 12-bit output, ddr mode ......................... 15 figure 2. 14-bit output, ddr mode ......................... 15 figure 3. 12-bit output, sdr mode ......................... 15 figure 4. data timing ............................................ 15 serial interface ..................................................... 16 timing diagram .................................................... 16 figure 5. serial port interface timing diagram ..... 16 table 1. serial port interface timing defnitions ... 16 register initialization ............................................. 16 serial register map .......................................... 17-18 table 2. summary of functions supported by serial interface ................................ 17-18 description of serial registers ........................ 18-25 table 3. software reset ......................................... 18 table 4. power-down modes .................................. 18 table 5. lvds drive strength programmability ......... 19 table 6. lvds output drive strength for lclk, fclk, and data ............................... 19 table 7. lvds internal termination programmability ....................................... 20 table 8. lvds output internal termination .............. 20 table 9. analog input invert ................................... 20 table 10. lvds test patterns .................................. 21 table 11. programmable gain ................................. 21 table 12. gain setting for channels 1-8 .................. 22 table 13. lvds clock programmability and data output modes ................................. 22 figure 6. phase programmability modes for lclk ..... 23 figure 7. sdr interface modes ............................... 23 table 14. number of serial output bits ................... 23 figure 8. lvds output timing adjustment .............. 24 table 15. full scale control .................................... 24 table 16. register values with corresponding charge in full-scale range ...................... 25 table 17. clock frequency ...................................... 25 table 18. clock frequency settings ......................... 25 table 19. performance control ................................ 25 table 20. performance control settings ................... 26 table 21. external common mode voltage buffer driving strength ........................... 26 theory of operation ............................................. 27 recommended usage ........................................... 27 analog input ......................................................... 27 figure 9. input confguration diagram ................ 27 dc-coupling .......................................................... 27 figure 10. dc-coupled input .............................. 27 ac-coupling .......................................................... 28 figure 11. transformer coupled input ................. 28 figure 12. ac-coupled input .............................. 28 figure 13. alternative input network ................... 28 clock input and jitter considerations ...................... 29 mechanical dimensions ................................... 30-31 qfn-64 package .................................................... 30 tqfp-80 package .................................................. 31 data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 3/31 rev 1c ordering information part number speed package pb-free rohs compliant operating temperature range packaging method cdk8307aitq80 20msps tqfp-80 yes yes -40c to +85c tray CDK8307AILP64 20msps qfn-64 yes yes -40c to +85c tray cdk8307bitq80 40msps tqfp-80 yes yes -40c to +85c tray cdk8307bilp64 40msps qfn-64 yes yes -40c to +85c tray cdk8307citq80 50msps tqfp-80 yes yes -40c to +85c tray cdk8307cilp64 50msps qfn-64 yes yes -40c to +85c tray cdk8307ditq80 65msps tqfp-80 yes yes -40c to +85c tray cdk8307dilp64 65msps qfn-64 yes yes -40c to +85c tray cdk8307eitq80 80msps tqfp-80 yes yes -40c to +85c tray cdk8307eilp64 80msps qfn-64 yes yes -40c to +85c tray moisture sensitivity level for qfn package is msl-2a, for tqfp package is msl-3. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 4/31 rev 1c pin confgurations qfn-64 cdk8307 qfn-64 2 in1 4 ip2 3 avss 1 ip1 6 avss 8 in3 7 ip3 16 d1n 9 avss 5 in2 10 ip4 12 dvss 14 dvss 13 pd 15 d1p 11 in4 47 ip8 45 in7 46 avss 48 in8 43 avss 41 ip6 42 in6 33 d8p 40 avss 44 ip7 39 in5 37 avss 35 dvdd 36 dvss 34 d8n 38 ip5 18 d2n 20 d3n 19 d3p 17 d2p 22 d4n 24 fclkn 23 fclkp 32 d7n 25 lclkp 21 d4p 26 lclkn 28 d5n 30 d6n 29 d6p 31 d7p 27 d5p 63 sclk 61 csn 62 sdata 64 resetn 59 clkn 57 avdd 58 clkp 49 avdd 56 nc 60 ovdd 55 nc 53 vcm 51 nc 52 avss 50 avdd 54 nc cdk8307 tqfp-80 2 ip1 4 avss 3 in1 1 avdd 6 in2 8 avss 7 avdd 20 lclkn 9 ip3 5 ip2 10 in3 12 ip4 14 avdd 13 in4 15 dvss 16 pd 18 dvss 17 dvss 19 lclkp 11 avss 59 in8 57 avss 58 ip8 60 avdd 55 ip7 53 avss 54 avdd 41 fclkp 52 in6 56 in7 51 ip6 49 in5 47 avdd 48 ip5 46 dvss 45 resetn 43 dvss 44 dvss 42 fclkn 50 avss 22 d1n 24 d2n 23 d2p 21 d1p 26 dvss 28 d3n 27 d3p 40 d8n 29 d4p 25 dvdd 30 d4n 32 d5n 34 d6n 33 d6p 35 dvdd 36 dvss 38 d7n 37 d7p 39 d8p 31 d5p 79 avss 77 sdata 78 sclk 80 avss 75 ovdd 73 avss 74 avss 61 avss 72 clkn 76 csn 71 clkp 69 nc 67 nc 68 avss 66 nc 65 vcm 63 avdd 64 nc 62 nc 70 avdd tqfp-80 tp tp data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 5/31 rev 1c pin assignments - qfn pin no. pin name description qfn-64 49, 50, 57 avdd analog power supply, 1.8v 3, 6, 9, 37, 40, 43, 46 avss analog ground 1 ip1 positive differential input signal, channel 1 2 in1 negative differential input signal, channel 1 4 ip2 positive differential input signal, channel 2 5 in2 negative differential input signal, channel 2 7 ip3 positive differential input signal, channel 3 8 in3 negative differential input signal, channel 3 10 ip4 positive differential input signal, channel 4 11 in4 negative differential input signal, channel 4 38 ip5 positive differential input signal, channel 5 39 in5 negative differential input signal, channel 5 41 ip6 positive differential input signal, channel 6 42 in6 negative differential input signal, channel 6 44 ip7 positive differential input signal, channel 7 45 in7 negative differential input signal, channel 7 47 ip8 positive differential input signal, channel 8 48 in8 negative differential input signal, channel 8 12, 14, 36 dvss digital ground 35 dvdd digital and i/o power supply, 1.8v 13 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature. 15 d1p lvds channel 1, positive output 16 d1n lvds channel 1, negative output 17 d2p lvds channel 2, positive output 18 d2n lvds channel 2, negative output 19 d3p lvds channel 3, positive output 20 d3n lvds channel 3, negative output 21 d4p lvds channel 4, positive output 22 d4n lvds channel 4, negative output 27 d5p lvds channel 5, positive output 28 d5n lvds channel 5, negative output 29 d6p lvds channel 6, positive output 30 d6n lvds channel 6, negative output 31 d7p lvds channel 7, positive output 32 d7n lvds channel 7, negative output 33 d8p lvds channel 8, positive output 34 d8n lvds channel 8, negative output 23 fclkp lvds frame clock (1x), positive output 24 fclkn lvds frame clock (1x), negative output 25 lclkp lvds bit clock, positive output data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 6/31 rev 1c pin no. pin name description 26 lclkn lvds bit clock, negative output 51, 54, 55, 56 nc not connected 52 tp test pin. leave open (un-connected) or connect to gnd. 53 vcm common mode output pin, 0.5 avdd 58 clkp positive differential input clock 59 clkn negative differential input clock. 60 ovdd digital cmos inputs supply voltage (1.7v to 3.6v) 61 csn chip select enable. active low. 62 sdata serial data input 63 sclk serial clock input 64 resetn reset spi interface pin assignments qfn (continued) data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 7/31 rev 1c pin no. pin name description tqfp 1, 7, 14, 47, 54, 60, 63, 70 avdd analog power supply, 1.8v 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 avss analog ground 2 ip1 positive differential input signal, channel 1 3 in1 negative differential input signal, channel 1 5 ip2 positive differential input signal, channel 2 6 in2 negative differential input signal, channel 2 9 ip3 positive differential input signal, channel 3 10 in3 negative differential input signal, channel 3 12 ip4 positive differential input signal, channel 4 13 in4 negative differential input signal, channel 4 48 ip5 positive differential input signal, channel 5 49 in5 negative differential input signal, channel 5 51 ip6 positive differential input signal, channel 6 52 in6 negative differential input signal, channel 6 55 ip7 positive differential input signal, channel 7 56 in7 negative differential input signal, channel 7 58 ip8 positive differential input signal, channel 8 59 in8 negative differential input signal, channel 8 15, 17, 18, 26, 36, 43, 44, 46 dvss digital ground 25, 35 dvdd digital and i/o power supply, 1.8v 16 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature. 19 lckp lvds bit clock, positive output 20 lckn lvds bit clock, negative output 21 d1p lvds channel 1, positive output 22 d1n lvds channel 1, negative output 23 d2p lvds channel 2, positive output 24 d2n lvds channel 2, negative output 27 d3p lvds channel 3, positive output 28 d3n lvds channel 3, negative output 29 d4p lvds channel 4, positive output 30 d4n lvds channel 4, negative output 31 d5p lvds channel 5, positive output 32 d5n lvds channel 5, negative output 33 d6p lvds channel 6, positive output 34 d6n lvds channel 6, negative output 37 d7p lvds channel 7, positive output 38 d7n lvds channel 7, negative output 39 d8p lvds channel 8, positive output 40 d8n lvds channel 8, negative output pin assignments - tqfp data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 8/31 rev 1c pin assignments - tqfp (continued) pin no. pin name description 41 fclkp lvds frame clock (1x), positive output 42 fclkn lvds frame clock (1x), negative output 45 resetn reset spi interface 61 tp test pin. leave open (un-connected) or connect to gnd. 62, 64, 66, 67, 69 nc not connected 65 vcm common mode output pin, 0.5 avdd 71 clkp positive differential input clock 72 clkn negative differential input clock. 75 ovdd digital cmos inputs supply voltage (1.7v to 3.6v) 76 csn chip select enable. active low. 77 sdata serial data input 78 sclk serial clock input data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 9/31 rev 1c absolute maximum ratings the safety of the device is not guaranteed when it is operated above the absolute maximum ratings. the device should not be operated at these absolute limits. adhere to the recommended operating conditions for proper device function. the information contained in the electrical characteristics tables and typical performance plots refect the operating conditions noted on the tables and plots. parameter reference pin min max unit avdd avss -0.3 +2.3 v dvdd dvss -0.3 +2.3 v ovdd avss -0.3 +3.9 v avss, dvss dvss / avss -0.3 +0.3 v analog inputs and outpts (ipx, inx) avss -0.3 +2.3 v clkx avss -0.3 +3.9 v lvds outputs dvss -0.3 +2.3 v digital inputs dvss -0.3 +3.9 v reliability information parameter min typ max unit junction temperature tbd c storage temperature range -60 +150 c lead temperature (soldering, 10s) j-std-020 esd protection product qfn-64 human body model (hbm) 2kv charged device model (cdm) 500v recommended operating conditions parameter min typ max unit operating temperature range -40 +85 c this device can be damaged by esd. even though this product is protected with state-of-the-art esd protection circuitry, damage may occur if the device is not handled with appropriate precautions. esd damage may range from device failure to performance degradation. analog circuitry may be more susceptible to damage as vary small parametric changes can result in specifcation noncompliance. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 10/31 rev 1c electrical characteristics (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 50msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14-bit output, unless otherwise noted) symbol parameter conditions min typ max units dc accuracy no missing codes guaranteed offset error offset error after digital offset cancellation 1 lsb gain error 6 %fs gain matching gain matching between channels. 3sigma value at worst case conditions. 0.5 %fs dnl differential non-linearity 12-bit level 0.2 lsb inl integral non-linearity 12-bit level 0.6 lsb v cmo common mode voltage output v avdd /2 v analog input v cmi input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v v fsr full scale range differential input voltage range 2.0 v pp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply avdd analog supply voltage 1.7 1.8 2.0 v dvdd digital supply voltage (up to 65msps) digital and output driver supply voltage 1.7 1.8 2.0 v digital supply voltage (above 65msps) digital and output driver supply voltage 1.8 1.9 2.0 v ovdd digital cmos input supply voltage 1.7 1.8 3.6 v electrical characteristics - cdk8307a (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 20msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 70 72.2 dbfs f in = 30mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8mhz 69 71.5 dbfs f in = 30mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc hd2 second order harmonic distortion f in = 8mhz 85 95 dbc f in = 30mhz 95 dbc hd3 third order harmonic distortion f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc enob effective number of bits f in = 8mhz 11.6 bits f in = 30mhz 11.5 bits crosstalk see note (1) on page 13 95 dbc power supply analog supply current 47 ma digital supply current digital and output driver supply 54 ma analog power dissipation 84 mw digital power dissipation 97 mw total power dissipation 180 mw power down dissipation power down mode 10 w sleep mode dissipation deep sleep mode 30 mw data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 11/31 rev 1c symbol parameter conditions min typ max units sleep channel mode dissipation all channels. in sleep ch. mode (light sleep) 46 mw sleep channel mode savings power dissipation savings per channel off 17 mw clock inputs maximum conversion rate 20 msps minimum conversion rate 15 msps electrical characteristics - cdk8307b (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 40msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 70 72.2 dbfs f in = 30mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8mhz 69 71.5 dbfs f in = 30mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc hd2 second order harmonic distortion f in = 8mhz 85 95 dbc f in = 30mhz 95 dbc hd3 third order harmonic distortion f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc enob effective number of bits f in = 8mhz 11.6 bits f in = 30mhz 11.5 bits crosstalk see note (1) on page 13 95 dbc power supply analog supply current 90 ma digital supply current digital and output driver supply 67 ma analog power dissipation 162 mw digital power dissipation 120 mw total power dissipation 280 mw power down dissipation power down mode 10 w sleep mode dissipation deep sleep mode 41 mw sleep channel mode dissipation all channels. in sleep ch. mode (light sleep) 71 mw sleep channel mode savings power dissipation savings per channel off 26 mw clock inputs maximum conversion rate 40 msps minimum conversion rate 20 msps electrical characteristics - cdk8307c (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 50msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 70 72.2 dbfs f in = 30mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8mhz 69 71.5 dbfs f in = 30mhz 70.7 dbfs data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 12/31 rev 1c symbol parameter conditions min typ max units sfdr spurious free dynamic range f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc hd2 second order harmonic distortion f in = 8mhz 85 95 dbc f in = 30mhz 95 dbc hd3 third order harmonic distortion f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc enob effective number of bits f in = 8mhz 11.6 bits f in = 30mhz 11.5 bits crosstalk see note (1) on page 13 95 dbc power supply analog supply current 111 ma digital supply current digital and output driver supply 73 ma analog power dissipation 200 mw digital power dissipation 132 mw total power dissipation 331 mw power down dissipation power down mode 10 w sleep mode dissipation deep sleep mode 46 mw sleep channel mode dissipation all channels. in sleep ch. mode (light sleep) 83 mw sleep channel mode savings power dissipation savings per channel off 31 mw clock inputs maximum conversion rate 50 msps minimum conversion rate 20 msps electrical characteristics - cdk8307d (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 65msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 14-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 70 72.2 dbfs f in = 30mhz 71.5 dbfs sinad signal to noise and distortion ratio f in = 8mhz 69 71.5 dbfs f in = 30mhz 70.7 dbfs sfdr spurious free dynamic range f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc hd2 second order harmonic distortion f in = 8mhz 85 95 dbc f in = 30mhz 95 dbc hd3 third order harmonic distortion f in = 8mhz 75 82 dbc f in = 30mhz 77 dbc enob effective number of bits f in = 8mhz 11.6 bits f in = 30mhz 11.5 bits crosstalk see note (1) on page 13 95 dbc power supply analog supply current 143 ma digital supply current digital and output driver supply 83 ma analog power dissipation 257 mw digital power dissipation 149 mw total power dissipation 405 mw power down dissipation power down mode 10 w sleep mode dissipation deep sleep mode 54 mw sleep channel mode dissipation all channels. in sleep ch. mode (light sleep) 103 mw data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 13/31 rev 1c symbol parameter conditions min typ max units sleep channel mode savings power dissipation savings per channel off 38 mw clock inputs maximum conversion rate 65 msps minimum conversion rate 20 msps electrical characteristics - cdk8307e (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 80msps clock, 50% clock duty cycle, -1dbfs 8mhz input signal, 12-bit output, unless otherwise noted) symbol parameter conditions min typ max units performance snr signal to noise ratio f in = 8mhz 68.5 70.1 dbfs f in = 30mhz 70 dbfs sinad signal to noise and distortion ratio f in = 8mhz 68 69.6 dbfs f in = 30mhz 69.5 dbfs sfdr spurious free dynamic range f in = 8mhz 74 77 dbc f in = 30mhz 76 dbc hd2 second order harmonic distortion f in = 8mhz 85 90 dbc f in = 30mhz 90 dbc hd3 third order harmonic distortion f in = 8mhz 75 77 dbc f in = 30mhz 76 dbc enob effective number of bits f in = 8mhz 11.3 bits f in = 30mhz 11.3 bits crosstalk see note (1) on page 13 95 dbc power supply analog supply current 173 ma digital supply current digital and output driver supply 88 ma analog power dissipation 312 mw digital power dissipation 158 mw total power dissipation 470 mw power down dissipation power down mode 10 w sleep mode dissipation deep sleep mode 56 mw sleep channel mode dissipation all channels. in sleep ch. mode (light sleep) 116 mw sleep channel mode savings power dissipation savings per channel off 44 mw clock inputs maximum conversion rate 80 msps minimum conversion rate 40 msps digital and timing electrical characteristics (avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, unless otherwise noted) symbol parameter conditions min typ max units clock inputs duty cycle 20 80 %high compliance cmos, lvds, lvpecl input range, differential differential input swing 200 mv pp input range, sine differential input swing, sine wave clock input 800 mv pp input range, cmos clkn connected to ground v ovdd mv pp input common mode voltage keep voltages within gnd and voltage of ovdd 0.3 v ovdd -0.3 v input capacitance differential 2 pf data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 14/31 rev 1c symbol parameter conditions min typ max units logic inputs (cmos) v ih high level input voltage v ovdd 3.0v 2 v v ovdd = 1.7v C 3.0v 0.8 ? v ovdd v v il low level input voltage v ovdd 3.0v 0 0.8 v v ovdd = 1.7v C 3.0v 0 0.2 ? v ovdd v i ih high level input leakage current 10 a i il low level input leakage current 10 a c i input capacitance 3 pf data outputs (lvds) compliance lvds v out differential output voltage 350 mv v cm output common mode voltage 1.2 v output coding default/optional offset binary/2s complement timing characteristics t ap aperture delay 0.8 ns rms aperture jitter <0.5 ps t pd start up time from power down start up time from power down to active mode. references have reached 99% of fnal value. (see section clock frequency) 260 992 clock cycles 15 s t slp startup time from sleep start up time from sleep mode to active mode 0.5 s t ovr out of range recovery time 1 clk cycles t lat pipeline delay 14 clk cycles lvds output timing characterisctics t data lclk to data delay time excluding programmable phase shift 250 ps t prop clock propogation delay 7 ? t lvds +2.6 7 ? t lvds +3.5 7 ? t lvds +4.2 ns lvds bit-clock duty-cycle 45 55 % lclk cycle frame clock cycle-to-cycle jitter 2.5 % lclk cycle t edge data rise- and fall time calculated from 20% to 80% 0.4 ns t clkedge clock rise- and fall time calculated from 20% to 80% 0.4 ns note: (1) signal applied to 7 channels (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 8mhz, f in0 = 9.9mhz (2) the outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 15/31 rev 1c lclkp lclkn dxx<1:0> t data t lvds t lvds /2 lclkp lclkn fclkn fclkp dxx<1:0> adc clock analog input d10 n-2 d11 n-2 d0 n-1 d1 n-1 d2 n-1 d3 n-1 d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d0 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n d8 n d9 n d10 n t lvds t prop lclkp lclkn fclkn fclkp dxx<1:0> adc clock analog input d0 n-1 d1 n-1 d2 n-1 d3 n-1 d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d12 n-1 d13 n-1 d1 n d3 n d2 n d5 n d0 n d4 n d6 n d7 n d8 n d9 n d10 n d11 n d12 n d13 n t lvds t prop lclkp lclkn fclkn fclkp dxx<1:0> adc clock analog input d10 n-2 d11 n-2 d0 n-1 d1 n-1 d2 n-1 d3 n-1 d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d1 n d3 n d2 n d5 n d0 n d4 n d6 n d7 n d8 n d9 n d10 n t lvds t prop lvds timing diagrams figure 1. 12-bit output, ddr mode figure 2. 14-bit output, ddr mode figure 3. 12-bit output, sdr mode figure 4. data timing data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 16/31 rev 1c serial interface the cdk8307 confguration registers can be accessed through a serial interface formed by the pins sdata (serial interface data), sclk (serial interface clock) and csn (chip select, active low). the following occurs when csn is set low: n serial data are shifted into the chip n at every rising edge of sclk, the value present at sdata is latched n sdata is loaded into the register every 24th rising edge of sclk multiples of 24-bit words data can be loaded within a single active csn pulse. if more than 24 bits are loaded into sdata during one active csn pulse, only the frst 24 bits are kept. the excess bits are ignored. every 24-bit word is divided into two parts: n the frst eight bits form the register address n the remaining 16 bits form the register data acceptable sclk frequencies are from 20mhz down to a few hertz. duty-cycle does not have to be tightly controlled. timing diagram figure 5 shows the timing of the serial port interface. table 1 explains the timing variables used in the timing diagram. csn a7 t cs t lo t h t hi t clk t s t ch t ch i a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk sdata figure 5. serial port interface timing diagram table 1. serial port interface timing defnitions parameter description minimum value unit t cs setup time between csn and sclk 8 ns t ch hold time between csn and sclk 8 ns t hi sclk high time 20 ns t lo sclk low time 20 ns t clk sclk period 50 ns t s data setup time 5 ns t h data hold time 5 ns register initialization before cdk8307 can be used, the internal registers must be initialized to their default values and power down must be activated. this can be done immediately after applying supply voltage to the circuit. register initialization can be done in one of two ways: 1. by applying a low-going pulse (minimum 20ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the rst bit high. internal registers are reset to default values when this bit is set. the rst bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down initialization can be done in one of two ways: 1. by applying a high-going pulse (minimum 20ns) on the pd pin (asynchr onous). 2. by cycling the spi register 0fhex pd bit to high (reg value '0200'hex) and then low (reg value '0000'hex). chi data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 17/31 rev 1c name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex rst software reset. this bit is self-clearing inactive x 00 pd_ch<8:1> channel-specifc power-down inactive x x x x x x x x 0f sleep go to sleep-mode inactive x pd go to power-down inactive x pd_pin_cfg<1:0> confgures the pd pin for sleep-modes pd pin confgured for power-down mode x x ilvds_lclk<2:0> lvds current drive programma - bility for lclkp and lclkn pins 3.5ma drive x x x 11 ilvds_ frame<2:0> lvds current drive programma - bility for fclkp and fclkn pins 3.5ma drive x x x ilvds_dat<2:0> lvds current drive programma - bility for output data pins 3.5ma drive x x x en_lvds_term enables internal termination for lvds buffers termination disabled x 12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers termination disabled 1 x x x term_ frame<2:0> programmable termination for fclkn and fclkp buffers termination disabled 1 x x x term_dat<2:0> programmable termination for output data buffers termination disabled 1 x x x invert_ch<8:1> swaps the polarity of the analog input pins electrically ipx is positive input x x x x x x x x 24 en_ramp enables a repeating full-scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_pat enable the mode wherein the output toggles between two defned codes inactive 0 x 0 single_custom_ pat enables the mode wherein the output is a constant specifed code inactive 0 0 x bits_cus - tom1<13:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the lsb inactive x x x x x x x x x x x x x x 26 bits_cus - tom2<13:0> bits for the second code of the dual custom pattern inactive x x x x x x x x x x x x x x 27 gain_ch1<3:0> programmable gain for channel 1 0db gain x x x x 2a gain_ch2<3:0> programmable gain for channel 2 0db gain x x x x gain_ch3<3:0> programmable gain for channel 3 0db gain x x x x gain_ch4<3:0> programmable gain for channel 4 0db gain x x x x gain_ch5<3:0> programmable gain for channel 5 0db gain x x x x 2b gain_ch6<3:0> programmable gain for channel 6 0db gain x x x x gain_ch7<3:0> programmable gain for channel 7 0db gain x x x x gain_ch8<3:0> programmable gain for channel 8 0db gain x x x x serial register map table 2. summary of functions supported by the serial interface data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 18/31 rev 1c name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex phase_ddr<1:0> controls the phase of lclk output relative to data 90 degrees x x 42 pat_deskew enable deskew pattern mode inactive 0 x 45 pat_sync enable sync pattern mode inactive x 0 btc_mode binary two's complement format for adc output data straight offset binary x 46 msb_frst serialized adc output data comes out with msb frst lsb-frst output x en_sdr enable sdr output mode. lclk becomes a 12x input clock ddr output mode x fall_sdr controls whether the lclk ris - ing or falling edge comes in the middle of the data window when operating in sdr mode rising edge of lclk comes in the middle of the data window x 1 perfm_cntrl<2:0> adc performance control nominal x x x 50 ext_vcm_bc<1:0> vcm buffer driving strength control nominal x x lvds_pd_mode controls lvds power down mode high z mode x 52 lvds_num_bits sets the number of lvds output bits 12-bit x 53 lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 55 clk_freq<1:0> input clock frequency 65mhz x x 56 description of serial registers table 3. software reset name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex rst self-clearing software reset inactive x 00 setting the rst register bit to '1', resets all internal registers including the rst register bit itself. table 4. power-down modes name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex pd_ch<8:1> channel-specifc power-down inactive x x x x x x x x 0f sleep go to sleep-mode inactive x pd go to power-down inactive x pd_pin_cfg<1:0> confgures the pd pin for sleep-mode pd pin confg - ured for power- down mode x x lvds_pd_mode controls lvds power down mode high z mode x 52 table 2. summary of functions supported by the serial interface (continued) data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 19/31 rev 1c setting pd_ch ?2009-2013 exar corporation 20/31 rev 1c table 7. lvds internal termination programmability name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex en_lvds_term enables internal termination for lvds buffers termination disabled x 12 term_lclk<2:0> programmable termination for lclkn and lclkp buffers termination disabled 1 x x x term_ frame<2:0> programmable termination for fclkn and fclkp buffers termination disabled 1 x x x term_dat<2:0> programmable termination for dxp and dxn buffers termination disabled 1 x x x the off-chip load on the lvds buffers may represent a characteristic impedance that is not perfectly matched with the pcb traces. this may result in refections back to the lvds outputs and loss of signal integrity. this effect can be mitigated by enabling an internal termination between the positive and negative outputs of each lvds buffer. internal termination mode can be selected by setting the en_lvds_term bit to '1'. once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. table 8 shows how the internal termination of the lvds buffers are programmed. the values are typical values and can vary by up to 20% from device to device and across temperature. table 8. lvds output internal termination for lclk, fclk, and data term_*<2:0> lvds internal termination 000 termination disabled 001 280 010 165 011 100 100 125 101 82 110 67 111 56 table 9. analog input invert name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex invert_ch<8:1> swaps the polarity of the analog input pins electrically ipx is positive input x x x x x x x x 24 the ipx pin represents the positive analog input pin, and inx represents the negative (complementary) input. setting the bits marked invert_ch <8:1> (individual control for each channel) causes the inputs to be swapped. inx would then represent the positive input, and ipx the negative input. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 21/31 rev 1c table 10. lvds test patterns name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex en_ramp enables a repeating full-scale ramp pattern on the outputs inactive x 0 0 25 dual_custom_pat enable the mode wherein the output toggles between two defned codes inactive 0 x 0 single_custom_ pat enables the mode wherein the output is a constant specifed code inactive 0 0 x bits_cus - tom1<13:0> bits for the single custom pattern and for the frst code of the dual custom pattern. <0> is the lsb inactive x x x x x x x x x x x x x x 26 bits_cus - tom2<13:0> bits for the second code of the dual custom pattern inactive x x x x x x x x x x x x x x 27 pat_deskew enable deskew pattern mode inactive 0 x 45 pat_sync enable sync pattern mode inactive x 0 to ease the lvds synchronization setup of cdk8307, several test patterns can be set up on the outputs. normal adc data are replaced by the test pattern in these modes. setting en_ramp to '1' sets up a repeating full-scale ramp pattern on all data outputs. the ramp starts at code zero and is increased 1lsb every clock cycle. it returns to zero code and starts the ramp again after reaching the full-scale code. a constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value in bits_custom1<13:0> . in this mode, bits_custom1<13:0> replaces the adc data at the output, and is controlled by lsb-frst and msb-frst modes in the same way as normal adc data are. the device may also be made to alternate between two codes by programming dual_custom_pat to '1'. the two codes are the contents of bits_custom1<13:0> and bits_custom2<13:0>. two preset patterns can also be selected: 1. deskew pattern: set using pat_deskew, this mode replaces the adc output with '01010101010101' (two lsbs removed in 12 bit mode). 2. sync pattern: set using pat_sync, the normal adc word is replaced by a fxed 1111110000000 word. note: only one of the above patterns should be selected at the same time. table 11. programmable gain name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex gain_ch1<3:0> programmable gain for channel 1 0db gain x x x x 2a gain_ch2<3:0> programmable gain for channel 2 0db gain x x x x gain_ch3<3:0> programmable gain for channel 3 0db gain x x x x gain_ch4<3:0> programmable gain for channel 4 0db gain x x x x gain_ch5<3:0> programmable gain for channel 5 0db gain x x x x 2b gain_ch6<3:0> programmable gain for channel 6 0db gain x x x x gain_ch7<3:0> programmable gain for channel 7 0db gain x x x x gain_ch8<3:0> programmable gain for channel 8 0db gain x x x x cdk8307 includes a purely digital programmable gain option in addition to the full-scale control. the programmable gain of each channel can be individually set using a set of four bits, indicated as gain_chn<3:0> for channel x. the gain setting is coded in binary from 0db to 12db, as shown in table 12 on the following page. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 22/31 rev 1c table 12. gain setting for channels 1-8 gain_chx<3:0> channel x gain setting 0000 0db 0001 1db 0010 2db 0011 3db 0100 4db 0101 5db 0110 6db 0111 7db 1000 8db 1001 9db 1010 10db 1011 11db 1100 12db 1101 do not use 1110 do not use 1111 do not use table 13. lvds clock programmability and data output modes name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex phase_ddr<1:0> controls the phase of lclk out - put relative to data 90 degrees x x 42 btc_mode binary two's complement format for adc output data straight offset binary x 46 msb_frst serialized adc output data comes out with msb frst lsb-frst output x en_sdr enable sdr output mode. lclk becomes a 12x input clock ddr output mode x fall_sdr controls whether the lclk ris - ing or falling edge comes in the middle of the data window when operating in sdr mode rising edge of lclk comes in the middle of the data window x 1 the output interface of cdk8307 is normally a ddr interface, with the lclk rising and falling edge transitions in the middle of alternate data windows. the phase for lclk can be programmed relative to the output frame clock and data using bits phase_ddr<1:0>. the lclk phase modes are shown in figure 6. the default timing is identical to setting phase_ddr<1:0> = '10'. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 23/31 rev 1c figure 6. phase programmability modes for lclk the device can also be made to operate in sdr mode by setting the en_sdr bit to '1'. the bit clock (lclk) is output at 12x times the input clock in this mode, two times the rate in ddr mode. depending on the state of fall_sdr, lclk may be output in either of the two manners shown in figure 7. as can be seen in figure 7, only the lclk rising (or falling) edge is used to capture the output data in sdr mode. the sdr mode is not recommended beyond 40msps because the lclk frequency becomes very high. en_sdr=?1?, fall_sdr_?0? en_sdr=?1?, fall_sdr_?1? fclkn fclkp lclkp lclkn dxx<1:0> fclkn fclkp lclkn lclkp dxx<1:0> figure 7. sdr interface modes the default data output format is offset binary. two's complement mode can be selected by setting the btc_mode bit to '1' which inverts the msb. the frst bit of the frame (following the rising edge of fclkp) is the lsb of the adc output for default settings. program - ming the msb_frst mode results in reverse bit order, and the msb is output as the frst bit following the fclkp rising edge. table 14. number of serial output bits name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex lvds_num_bits sets the number if lvds output bits 12-bit x 53 lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 phase_ddr<1:0>=?00? = 270 phase_ddr<1:0>=?01? =180 phase_ddr<1:0>=?10? = 90 (default) phase_ddr<1:0>=?11? = 0 fclkn fclkp lclkp lclkn dxx<1:0> fclkn fclkp lclkn lclkp dxx<1:0> fclkn fclkp lclkn lclkp dxx<1:0> fclkn fclkp lclkp lclkn dxx<1:0> data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 24/31 rev 1c the adc channels have 13 bits of resolution. there are two options for the serial lvds outputs, 12 bits or 14 bits, se - lected by setting lvds_num_bits to '0' or '1', respectively. in 12-bit mode, the lsb bit from the adcs are removed in the output stream. in 14-bit mode, a '0' is added in the lsb position. power down mode must be activated after or during a change in the number of output bits. to ease timing in the receiver when using multiple adc chips, the cdk8307 has the option to adjust the timing of the output data and the frame clock. the propagation delay with respect to the adc input clock can be moved one lvds clock cycle forward or backward, by using lvds_advance and lvds_delay , respectively. see fgure 8 for details. note that lclk is not affected by lvds_delay or lvds_advance settings. figure 8: lvds output timing adjustment table 15. full scale control name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex fs_cntrl<5:0> fine adjust adc full scale range 0% change x x x x x x 55 the full-scale voltage range of cdk8307 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. this leads to a maximum range of 10% adjustment. table 16 shows how the register settings correspond to the full-scale range. note that the values for full-scale range adjustment are approximate. the dac is, however, guaranteed to be monotonous. the full-scale control and the programmable gain features differ in two major ways: 1. the full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. the programmable gain feature has much coarser gain steps and larger range than the full-scale control. fclkp fclkn fclkp fclkn lclkp t lvds t lvds t lvds t prop t prop t prop default: lvds_delay = ?1?: lvds_advance = ?1?: *lvds output timing adjustment lclkn dxx<1:0> fclkp fclkn dxx<1:0> dxx<1:0> d3 n-1 d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d0 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n d8 n d9 n d2 n-1 d3 n-1 d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d0 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n d8 n d4 n-1 d5 n-1 d6 n-1 d7 n-1 d8 n-1 d9 n-1 d10 n-1 d11 n-1 d0 n d1 n d2 n d3 n d4 n d5 n d6 n d7 n d8 n d9 n d10 n data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 25/31 rev 1c table 16. register values with corresponding change in full-scale range fs_cntrl <5:0> full-scale range adjustment 111111 +9.7% ... ... 100001 +0.3% 100000 +0% 011111 -0.3% ... ... 000000 -10% table 17. clock frequency name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex clk_freq<1:0> input clock frequency 50 - 80mhz x x 56 to optimize startup time a register is provided where the input clock frequency can be set. some internal circuitry has startup times that are frequency independent. default counter values are set to accommodate these startup times at the maximum clock frequency. this will lead to increased startup times at low clock frequency. setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better ft the actual startup time, such that the startup time will be reduced. the start up times from power down mode and deep sleep mode are changed by this register setting. table 18. clock frequency settings clk_freq <1:0> clock frequency (mhz) startup delay (clock cycles) startup delay (s) 00 50 - 80 992 12.4 - 19.8 01 32.5 - 50 640 12.8 - 19.7 10 20 - 32.5 420 12.9 - 21 11 15 - 20 260 13 - 17.3 table 19. performance control name description default d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 address in hex perfm_ cntrl<2:0> adc performance control nominal x x x 50 ext_vcm_ bc<1:0> vcm buffer driving strength control nominal x x there are two registers that impact performance and power dissipation. the perfm_cntrl register adjusts the performance level of the adc core. if full performance is required, the nominal setting must be used. the lowest code can be used in situations where power dissipation is critical and performance is less important. for most conditions the performance at the minimum setting will be similar to nominal setting. however, only 10-bit performance can be expected at worst case conditions. the power dissipation savings shown in table 20 are only approximate numbers for the adc current alone. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 26/31 rev 1c table 20. performance control settings performance_control <2:0> power dissipation 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) nominal 001 do not use 010 do not use 011 do not use the ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the vcm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the vcm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. table 21. external common mode voltage buffer driving strength ext_vcm_bc <1:0> vcm buffer driving strength 00 off (vcm foating) 01 (default) low 10 high 11 max data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 27/31 rev 1c therory of operation the cdk8307 is an 8-channel, high-speed, cmos adc. the 13-bits given out by each channel are serialized to 12, 13 or 14-bits and sent out on a single pair of pins in lvds format. all eight channels of the cdk8307 operate from a single differential or single ended clock. the sam - pling clocks for each of the eight channels are generated from the clock input using a carefully matched clock buf - fer tree. the 12x/13x/14x clock required for the serializer is generated internally from fclk using a phase-locked loop (pll). a 6x/6.5x/7x and 1x clock are also output in lvds format, along with the data to enable easy data capture. the cdk8307 uses internally generated references that can be shorted across several devices to improve gain-matching. the differential reference value is 1v. this results in a differential input of -1v to correspond to the zero code of the adc, and a differential input of +1v to correspond to the full-scale code (code 8191). the adc employs a pipelined converter architecture. each stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at 13-bit level. the cdk8307 operates from two sets of supplies and grounds. the analog supply and ground set is identifed as avdd and avss, while the digital set is identifed by dvdd and dvss. recommended usage analog input the analog input to the cdk8307 is a switched capacitor track-and-hold amplifer optimized for differential opera - tion. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. the vcm pin provides a voltage suitable as common mode voltage reference. the internal buffer for the vcm voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_ bc<1:0> register. figure 9 shows a simplifed drawing of the input network. the signal source must have suffciently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. figure 9. input confguration diagram dc-coupling figure 10 shows a recommended confguration for dc- coupling. note that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ext output should be used as a reference to set the common mode voltage. the input amplifer could be inside a companion chip or it could be a dedicated amplifer. several suitable single ended to differential driver amplifers exist in the market. the system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the cdk8307 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 10 must be varied according to the recommendations for the driver. figure 10. dc-coupled input 33pf 43 43 data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 28/31 rev 1c ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 11 shows a recommended confguration using a transformer. make sure that a transformer with suffcient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to keep phase mismatch between the differential adc inputs small for good hd2 performance. this type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have adequate performance at high frequen - cies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. figure 11. transformer coupled input if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated prop - erly at the source side, they are refected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in figure 10 can be used. figure 12 shows ac-coupling using capacitors. resistors from the cm_ext output, rcm, should be used to bias the differential input signals to the correct voltage. the series capacitor, ci, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 12. ac-coupled input note that startup time from sleep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of figure 13 can be used. the confguration is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below nyquist. figure 13: alternative input network values of the series inductor will however depend on board design and conversion rate. in some instances a shunt ca - pacitor in parallel with the termination resistor (e.g. 33pf) may improve adc performance further. this capacitor attenuate the adc kick-back even more, and minimize the kicks traveling towards the source. however the impedance match seen into the transformer becomes worse. 33 33 r t 47 pf pf 120nh 120nh 33 33 r t 68 220 optional 1:1 data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 29/31 rev 1c clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in the cdk8307 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% is acceptable. the input clock can be supplied in a variety of formats. the clock pins are ac-coupled internally, and hence a wide common mode voltage range is accepted. differential clock sources as lvds, lvpecl or differential sine wave can be connected directly to the input pins. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. for differential sine wave clock input the amplitude must be at least 0.8v pp . the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation below. snr jitter = 20 ? log (2 ? ? f in ? t ) where f in is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable per - formance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost im - portance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter per - formance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re- timed with a low jitter master clock as the last operation before it is applied to the adc clock input. data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 30/31 rev 1c mechanical dimensions qfn-64 a a2 a3 a1 1 1.14 d d1 e e1 1.14 pin 1 id dia. 0.20 pin 1 id 0.05 dia. seating plane 0.45 g l l b e d2 e2 a c b aaa c a ccc c bbb c a aaa c b bbb c b f 0.10 m c b a notes: 1 . all dimensions are in millimeters. 2. die thickness allowable is 0.305mm maximum (.012 inches maximum) 3. dimensioning & tolerances conform to asme y14.5m. -1994. 4. dimension applies to plated terminal and is measured between 0.20 and 0.25mm from terminal tip. 5. the pin #1 identifier must be placed on the top surface of the package by using indentation mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max 0.08mm. 8. applied for exposed pad and terminals. exclude embedding part of exposed pad from measuring. 9. applied only to terminals. 10. package corners unless otherwise specipied are r0.1750.025mm. top view bottom view side view inches millimeters symbol min typ max min typ max a ? ? 0.035 ? ? 0.9 a 1 0.00 0.0004 0.002 0.00 0.01 0.05 a 2 ? 0.026 0.028 ? 0.65 0.7 a 3 0.008 ref 0.2 ref b 0.008 0.010 0.012 0.2 0.25 0.30 d 0.354 bsc 9.00 bsc d 1 0.354 bsc 8.75 bsc d 2 0.197 0.205 0.213 5.0 5.2 5.4 e 0.354 bsc 9.00 bsc e 1 0.344 bsc 8.75 bsc e 2 0.197 0.205 0.213 5.0 5.2 5.4 f 0.05 ? ? 1.3 ? ? g 0.0096 0.0168 0.024 0.24 0.42 0.6 l 0.012 0.016 0.020 0.3 0.4 0.5 e 0.020 bsc 0.50 bsc 1 0 ? 12 0 ? 12 tolerance of form and position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002 data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c ?2009-2013 exar corporation 31/31 rev 1c mechanical dimensions (continued) tqfp-80 note: each lead centerline is located within 0.08mm of its true position at maximum material condition. detail of lead end symbol dimensions (mm) a 1.20 a 1 0.10 0.05 a 2 1.00 0.05 a 3 0.25 b 0.22 0.05 c 0.145 +0.055 0.145 -0.045 d 12.00 0.20 e 12.00 0.20 e 0.50 hd 14.00 0.20 he 14.00 0.20 l 0.50 lp 0.60 0.15 l 1 1.00 0.20 x 0.08 y 0.08 zd 1.25 ze 1.25 3 +5 3 -3 tqfp-80 data sheet cdk8307 12/13-bit, 20/40/50/65/80msps, eight channel, ultra low power adc with lvds rev 1c for further assistance: exar corporation headquarters and sales offces 48720 kato road tel.: +1 (510) 668-7000 fremont, ca 94538 - usa fax: +1 (510) 668-7001 www.exar.com notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specifc application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. |
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